The present invention relates to DC-DC converters and, more particularly, to a self-driven, synchronous rectification scheme for a DC-DC power converter.
There is an ever-increasing demand in the power electronics market for low voltage and high current DC-DC converters. As output voltage is desired to be 3.3V or lower, even a state-of-the-art schottky diode with a forward voltage drop of 0.3V has an unacceptable amount of power loss.
Because of this, synchronous rectifier circuits are often used to improve the efficiency of DC-DC converters. Generally, there are two types of synchronous rectifier circuits, self-driven and externally driven. Since the self-driven mode is usually less complex, less costly and more reliable, it is preferred for use with most low voltage DC-DC converter applications.
FIG. 1(A) illustrates a conventional self-driven synchronous rectification, asymmetrical, zero voltage switching (ZVS) half-bridge (HB) topology which is only generally suitable for applications where the output voltage is in the range of from about 3.3V to 6V. Referring to FIG. 1B, the gate-drive voltages Vgs3 and Vgs4 of synchronous rectifiers (SRs) S3 and S4, respectively, are as follows: (1)                               V          gs3                =                                                            2                ⁢                                  N                  s                                                            N                p                                      ⁢            D            ⁢                          xe2x80x83                        ⁢                          V              in                                =                                                    2                N                            ⁢              D              ⁢                              xe2x80x83                            ⁢                              V                in                                      =                                                            V                  o                                                  1                  -                  D                                            ⁢                              xe2x80x83                            ⁢                              (                                                      t                    0                                    ≤                  t                  ≤                                      t                    1                                                  )                                                                        (        1        )                                          V          gs4                =                                                            2                ⁢                                  N                  s                                                            N                p                                      ⁢                          (                              1                -                D                            )                        ⁢                          V                              i                ⁢                                  xe2x80x83                                ⁢                n                                              =                                                                      2                  ⁢                                      (                                          1                      -                      D                                        )                                                  N                            ⁢                              V                                  i                  ⁢                                      xe2x80x83                                    ⁢                  n                                                      =                                                            V                  o                                D                            ⁢                              xe2x80x83                            ⁢                              (                                                      t                    1                                    ≤                  t                  ≤                                      t                    2                                                  )                                                                        (        2        )            
wherein, Vin is the input voltage; Vo is the output voltage; D is the steady-state duty cycle; Np is the number of primary winding turns of the transformer; Ns is the number of secondary turns of the transformer; and N is the turn ratio of the transformer. The turn ratio of the transformer TR is calculated by dividing the number of primary windings by the number of secondary windings (i.e. N=Np/Ns).
FIG. 1(B) illustrates the switching waveform occurring in the converter illustrated in FIG. 1(A). As shown in FIG. 1(B), the gate-drive voltage Vgs4 of S4 is always higher than the gate-drive voltage Vgs3 of S3 if D is less than 50%. If we assume that the minimum steady-state duty cycle D at heavy load is 30%, then Vgs3 is about 1.4V, and Vgs4 is about 3.3V. Since most synchronous rectifiers (including logic level devices) only work well with the gate-drive voltage between about 4V and 20V, the circuit shown in FIG. 1(A) only works well when the output voltage V0 is between 2.9V to 6V. If the output voltage is below 2.9V, S3 would be under driven. If the output voltage were above 6V, then S4 would be over driven. In either case the synchronous rectifiers are easily rendered inoperative.
FIG. 2(A) shows a circuit diagram of an asymmetrical ZVS HB converter incorporating the self-driven synchronous rectifier circuit of the invention disclosed in U.S. patent application Ser. No. 09/932,398, filed Aug. 17, 2001, the entire disclosure of which is incorporated by reference herein. The self-driven synchronous rectifier circuit of FIG. 2(A) includes two power switches S1 and S2; a transformer Tr having a primary winding Np, a secondary winding Ns and an auxiliary winding Na; two secondary synchronous rectifiers S3 and S4; two diodes D1 and D2; and two zener diodes ZD1 and ZD2.
In the circuit of FIG. 2(A), when S3 conducts, the gate-drive voltage of S4 is clamped by D1. Also, when S4 conducts, the gate-drive voltage of S3 is clamped by D2. In other words, D1 and D2 prevent S3 and S4 from conducting at the same time. ZD1 and ZD2 operate to restrain the gate over voltage of S3 and S4, respectively. Because of this circuit configuration, the self-driven synchronous rectifier circuit operates normally at various output voltages, such as low output voltages of 2.9V or lower and/or high output voltages above 6V.
FIG. 2(B) illustrates the switching waveform of the converter shown in FIG. 2(A). Vgs1 and Vgs2 represent the gate voltage waveforms of the two power switches S1 and S2. Vp is the primary voltage waveform of transformer Tr. VNa is the voltage waveform of the auxiliary winding. Vgs3 and Vgs4 represent the gate voltage waveforms of the two synchronous rectifiers S3 and S4. Vgs3 and Vgs4 are calculated as follows:                               V          gs3                =                                            N              a                                      N              p                                ⁢          D          ⁢                      xe2x80x83                    ⁢                      V                          i              ⁢                              xe2x80x83                            ⁢              n                                ⁢                      xe2x80x83                    ⁢                      (                                          t                0                            ≤              t              ≤                              t                1                                      )                                              (        3        )                                          V          gs4                =                                            N              a                                      N              p                                ⁢                      (                          1              -              D                        )                    ⁢                      V                          i              ⁢                              xe2x80x83                            ⁢              n                                ⁢                      xe2x80x83                    ⁢                      (                                          t                1                            ≤              t              ≤                              t                2                                      )                                              (        4        )            
wherein, D is the on-time of switch S1 in percent duty cycle; 1-D is the on-time of switch S2 in percent duty cycle; Np is the number of primary winding turns of transformer Tr; Na is the number of auxiliary winding turns of the transformer Tr; and Vin is the input voltage.
Comparing equations (3) and (4) above with equations (1) and (2), it can be seen, the gate voltage of self-driven synchronous rectifiers S3 and S4 may be adjusted by selecting the number of auxiliary winding turns Na of transformer Tr. This selection of the auxiliary number of winding turns Na ensures a reasonable gate-drive voltage for the synchronous rectifiers S3 and S4 even when the output voltage is lower than 2.9V or higher than 6V.
Conventionally, the demand for self-driven synchronous rectifier is satisfied by the second scheme. But as logic integrated circuits have migrated to lower working voltages, it is expected that the next generation of integrated circuits will require power supplies with voltage in the 1-2V range. This will confront the second self-driven scheme with great challenges. As shown in FIG. 2(A), in practical application the circuit has a premise:
2Nsxe2x89xa7Naxe2x80x83xe2x80x83(5)
A very low output voltage, namely 1.5V or less, would require a reduction in the number of turns of the winding Ns. However, a reduction in the number of turns of the winding Na would not ensure a reasonable gate drive voltage for the synchronous rectifiers. On the other hand, if the number of turns of the winding Na are made substantially greater than the number of turns of the winding Ns, i.e., if 2Nsxe2x89xa6Na the winding Na will short through the loop of Na, D1, S4 and ZD1 (or the loop of Na, D2, 2Ns, S3 and ZD2). If this occurs, the self-driven circuit shown in FIG. 2(A) will not work.
This invention discloses a novel self-driven scheme that overcomes the above-mentioned drawbacks of the prior art self-driven schemes.
A self-driven synchronous rectifier circuit in accordance with one aspect of the present invention includes an input circuit including a transformer having a primary winding for receiving a voltage, a secondary winding and an auxiliary winding. First and second synchronous rectifiers connected to the secondary winding of the transformer and responsive to the signal across the auxiliary winding are provided for selectively and alternatively turning the synchronous rectifiers ON and OFF. A first clamping circuit is provided for clamping the second synchronous rectifier when the first synchronous rectifier is turned ON and a second clamping circuit is provided for clamping the first synchronous rectifier when the second synchronous rectifier is turned ON. The first clamping circuit includes a first switching device operative to disable the first clamping circuit when the second clamping circuit is operative, and the second clamping circuit includes a second switching device operative to disable the second clamping circuit when the first clamping circuit is operative.
In accordance with another aspect, the self-driven synchronous rectification circuit of the present invention includes two power switches S1 and S2; a transformer Tr having a primary winding Np, a secondary winding Ns and an auxiliary winding Na; two secondary synchronous rectifiers S3 and S4; two diodes D1 and D2; and two zener diodes ZD1 and ZD2; and two switching transistors Q1 and Q2.
In the circuit of the present invention, when S3 conducts, the gate-drive voltage of S4 is clamped by D1 and Q1. Also, when S4 conducts, the gate-drive voltage of S3 is clamped by D2 and Q2. In other words, D1, Q1 and Q2 prevent S3 and S4 from conducting at the same time. ZD1 and ZD2 restrain the gate over voltage of S3 and S4, respectively.
Further, when the gate drive voltage of S4 is clamped by D1 and Q1, Q2 disables D2 and when the gate drive voltage of S3 is clamped by D2 and Q2, Q1 disables D1.